RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
control channel, add system overhead to the cell (including the PHY ID), and
then transmit the cell over both high speed links simultaneously. Per PHY rate
decoupling and flow control are implemented to ensure head-of-line blocking and
far-end buffer overflow never occur. Flow control signaling is implemented using
in-band system overhead appended to each cell sent over the LVDS link (see
Table 16).
The transmitted cell is identical on both links except for the ACTIVE field, the
BOC bit and UPCA status field. Stuff cells are automatically generated and sent
over the high speed link if there is no user data cell or control channel cell to
send or if the far-end is indicating that it has no room in any of its per channel
buffers.
It is important to note that the S/UNI-DUPLEX only acts on the CA and
UPCA status fields of the active LVDS receive link. The inactive link’s flow
control information is ignored. This should be taken into account when
designing 1:1 protected systems, especially with respect to the behavior of
the standby common card data path and the embedded control channel.
Rate decoupling between the external PHYs and the LVDS link occurs via the per
channel buffers. Specifically, independent internal processes determine how the
buffers are filled and how they are scheduled onto the LVDS link.
When the S/UNI-DUPLEX is configured as a parallel bus master the 32 PHY
devices are polled in a round robin fashion. When a polled external PHY
indicates that it has a cell available the cell is transferred into a shallow FIFO.
Each PHY has its own FIFO. If the per-channel flow control asserted by the far-
end prevents cells from being transferred from a buffer to the LVDS transmit link,
the buffer may fill to capacity, at which time the S/UNI-DUPLEX will remove that
external PHY from the polling sequence until buffer space becomes available.
Under congestion the S/UNI-DUPLEX does not discard cells, although the
external PHY device may have to.
When the S/UNI-DUPLEX is configured as a parallel bus slave the PHY devices
are polled by the bus master and the S/UNI-DUPLEX provides the appropriate
FIFO status indication, as described in Section 9.1.2 and Section 9.1.3. If the
per-channel flow control asserted by the far-end prevents cells from being
transferred from a buffer to the LVDS transmit link, the buffer may fill to capacity,
at which time the S/UNI-DUPLEX will deassert the buffer available status for that
PHY when it is polled. Under congestion the S/UNI-DUPLEX does not discard
cells, although the external bus master may have to.
When the S/UNI-DUPLEX is configured for clocked serial data interfaces, cells
from the maximum 16 PHYs are buffered in 16 dedicated logical channel FIFOs.
They should be programmed in the Transmit Logical Channel FIFO Depth
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
75
PMC [ PMC-SIERRA, INC ]
