RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
9.2.2 Downstream Functions
In the downstream direction (toward the modems), the S/UNI-DUPLEX uses one
clock input and one data output per channel to produce valid ATM cell streams
with correct HCS octets and inserted idle cells to adapt to the clock generated by
the modem.
Each modem provides its own clock, which may be asynchronous to all others.
The S/UNI-DUPLEX responds to the active edge of each transmit clock by
generating a single bit. Idle cells are automatically generated and interleaved with
the cells available from the high-speed serial interface to match the channel’s bit
rate as driven by the clock input.
When it needs to insert transmission overhead (such as framing bits) into the
data stream provided by the S/UNI-DUPLEX, the modem is expected to gap the
downstream clock provided to the S/UNI-DUPLEX so that no data bits are output
during the overhead bit period(s).
Optionally, the S/UNI-DUPLEX can be programmed (using register 0x74) to
optionally force octet alignment of the data to overhead by monitoring the clock
gaps. To support dynamically adaptable modem rate without external
intervention, the system automatically adapts to frequency changes on
LTXC[15:0]. When byte alignment is enabled, the clock gap period is monitored
on each LTXC[15:0] input. If the gap period is greater than the minimum
detectable period, the most significant bit of the data octet is output during the
gap period, allowing the receiving modem to receive it on the first clock active
edge after the gap.
The S/UNI-DUPLEX can detect clock gaps of eight clock periods over the
permitted LTXC[15:0] clock line frequency range. The frequency range over
which one bit framing gap can be detected changes linearly with the speed of the
high-speed links. When operating the LVDS interface at 200 Mb/s (REFCLK
frequency set to 25 MHz), the S/UNI-DUPLEX will detect one bit clock gap for a
line frequency range of 200 kHz to 8 MHz. At the minimum frequency of 100
Mb/s (REFCLK frequency of 12.5 MHz) the line frequency range at which one bit
framing gap can be detected is 100 kHz to 4 MHz.
As an option (see Transmit Serial Indirect Channel Data register 0x71) the
transmitted data stream can be provided clear channel by disabling HCS
generation and payload scrambling. It is the responsibility of the traffic
generation entity at the other end of the LVDS link to send traffic at a sufficient
rate to keep the internal FIFOs from emptying, else the clear channel data will be
interrupted by an automatically generated ATM idle cell pattern.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
62
PMC [ PMC-SIERRA, INC ]
