RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Byte
Bits
6
Mnemonic
Description
new code word.
Refer to the 9.3.1 section for more details.
3
ACTIVE
The link active bit indicates which of the
redundant links is currently chosen. The
S/UNI-DUPLEX will switch to the link which
contains a one in this location for at least 3
consecutive cells. The local
microprocessor can override this selection.
If both links present a one in this location,
the selection remains unchanged. To
confirm which link is active, the transmitted
ACTIVE bit will be a one if the associated
receive link is selected.
In the event of an errored header, the
previous ACTIVE value is retained.
3
5:0
TREF[5:0]
The timing reference encodes an 8 kHz
signal inband that is independent of the
serial bit rate.
The TREF[5:0] binary value represents the
number of high-speed link bytes after this
one at which the timing reference is
inferred. An all ones value indicates no
timing mark is associated with this cell.
The transmitter outputs are internally terminated current mode drivers. Correct
termination is at the receiver required to provide appropriated signal levels.
The internal transmit clock is synthesized from a 12.5 MHz to 25 MHz clock. The
resulting data bit rate is eight times the frequency of the REFCLK input. All jitter
below 1 MHz on REFCLK is passed unattenuated to the TXD1+/- and TXD2+/-
outputs. The design of the loop filter and PLL is optimized for minimum intrinsic
jitter. With a jitter free reference input and a low noise board layout, the intrinsic
jitter is typically less than 0.01 UI RMS and 0.10 UI peak-to-peak when measured
using a band pass filter with 12 kHz and 1.3 MHz cutoff frequencies.
The two truly differential receivers are capable of handling signal swings down to
100mV. A wide common mode range makes them compatible with LVDS signals.
External termination resisters must be provided to match the cable impedance.
The receivers monitor for loss of signal (LOS) on the links. LOS is declared upon
2048 bit periods (13.2 μs at 155.52 Mb/s) without a signal transition in the
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
66