RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Fig. 28: Microprocessor Interface Read Timing
A[6:0]
Valid Address
tS
tH
ALR
ALR
tV
L
tS
tH
LR
LR
ALE
tS
tH
AR
AR
(CSB+RDB)
tZ
tZ
INTH
tP
RD
RD
D[7:0]
Valid Data
Notes on Microprocessor Interface Read Timing:
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point.
2. Maximum output propagation delays are measured with a 100 pF load on the
Microprocessor Interface data bus, (D[7:0]).
3. A valid read cycle is defined as a logical OR of the CSB and the RDB signals.
4. In non-multiplexed address/data bus architectures, ALE should be held high so
parameters tS
, tH , tV , tH , and tS are not applicable.
ALR L LR LR
ALR
5. Parameter tH
is not applicable if address latching is used.
AR
6. When a set-up time is specified between an input and a clock, the set-up time is
the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point
of the clock.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
218
PMC [ PMC-SIERRA, INC ]
