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PM7350-PGI 参数 Datasheet PDF下载

PM7350-PGI图片预览
型号: PM7350-PGI
PDF下载: 下载PDF文件 查看货源
内容描述: [Support Circuit, 1-Func, CMOS, PBGA160, 15 X 15 MM, 1.81 MM HEIGHT, PLASTIC, BGA-160]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 245 页 / 898 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7350 S/UNI DUPLEX  
DATA SHEET  
PMC-1980581  
ISSUE 8  
DUAL SERIAL LINK PHY MULTIPLEXER  
12  
OPERATION  
12.1 Microprocessor Inband Communication  
In the upstream direction, the S/UNI-DUPLEX broadcasts control channel cells  
on both the active and spare high-speed serial links. The contents of the cells  
shall distinguish the two control channels if necessary. In the downstream  
direction, each high-speed serial link has a dedicated queue for the control  
channel cells.  
The S/UNI-DUPLEX includes hardware support for CRC-32 generation and  
verification. It consists of two accumulator registers, the Insert CRC-32  
Accumulator register for control channel in the upstream direction and the Extract  
CRC-32 Accumulator for control channel in the downstream direction. To allow  
context change, each accumulator register can be preset, read and written by the  
microprocessor.  
12.1.1 Inserting Cells Into Control Channels  
Cells are inserted into control channels by manipulating the Microprocessor  
Insert FIFO Control and Microprocessor Insert FIFO Ready registers. The  
following steps are required to insert a cell:  
1. Poll the INSRDY bit in the Microprocessor Insert FIFO Ready. Alternately,  
service the interrupts that result from setting the INSRDYE bit in the  
Microprocessor Cell Buffer Interrupt Control and Status register.  
2. If CRC-32 calculation is required set the INSCRCPR of the Microprocessor  
Insert FIFO Control register to logic 0 to enable the CRC-32 process. The  
Insert CRC-32 Accumulation register can be preset by writing a logic 1 to  
INSCRCPR prior to enabling the CRC-32 calculation.  
If the cell is not the first of the message, write the Insert CRC-32 Accumulator  
register with the value stored at the end of the previous cell for the same  
control channel. This step is not necessary if the last cell inserted belonged  
to the same control channel as the current cell.  
Insertion of the CRC-32 field is done by setting the INSCRCEND bit of the  
Microprocessor Insert FIFO Control register to logic 1 prior to writing the last  
cell of the CPCS-PDU. The S/UNI-DUPLEX will overwrite the data of the last  
four bytes of the cell payload written by the microprocessor with the ones  
complement of the content of the Insert CRC-32 Accumulator register.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
184  
 
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