RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
parallel bus, master bus mode or clocked serial data). Refer to the S/UNI-
VORTLEX datasheet for details.
• The parallel bus of the S/UNI-DUPLEX is fully compliant to Utopia Level 2 bus
protocol only when configured as a bus master. In this case, cell length is
either 53 bytes or 27 16-bit words depending if the interface bus width is set
to 8 or 16 bit.
• When used as a bus slave, the parallel bus input and output ports can
operate in SCI-PHY or Any-PHY mode. When configured as a SCI-PHY bus
slave, the input port can be remains compliant to Utopia Level 2 (default
setting), but the output port becomes a proxy, a single addressable PHY
carrying the cell traffic for up to the 32 PHYs. The PHY ID is encoded in a
system prepend byte or 16-bit word (depending if the interface bus width is
set to 8 or 16 bit). To keep the cell compatible with Utopia Level 2 format, the
PHY ID can be routed in the H5 (H5/UDF for 16-bit bus) field of the cell by
setting the INADDUDF bit of the SCI-PHY/Any-PHY Output Configuration
register to logic 1.
• When operating in SCI-PHY (master or slave mode) or in Any-PHY slave
mode, prepend words can be added to the cell, up to two bytes for the 8-bit
(PRELEN[1:0]=0b10) cell format and one word in 16-bit (PRELEN[1:0]=0b01)
cell format. The H5 (H5/UDF) field of the cell can be omitted as determined by
setting the H5UDF of the SCI-PHY/Any-PHY Input Configuration 1 and SCI-
PHY/Any-PHY Output Configuration registers to logic 0.
• Both input and output parallel interface can operate in Any-PHY mode,
meaning Any-PHY bus timing and addressing must be used. Setting the
INADDUDF bit of the register SCI-PHY/Any-PHY Output Configuration
register to 1 when the bus is configured as Any-PHY has no effect. Although
the S/UNI-DUPLEX only supports 32 logic channels, it is possible to specify
the base address of the input port in a larger addressing range with the
Extended Address Match and Extended Address Mask registers. The value of
the Extended Address Match register is also appended to the PHY ID of cells
read from the output port.
• For a given configuration set by the values of the H5UDF, INADDUDF and
PRELEN[1:0], cell length may vary depending of the mode of the parallel bus,
determined by the value of the IMASTER, IBUS8, IANYPPHY, OMASTER,
OBUS8 and OANYPHY inputs. The following is an example of the various cell
lengths produced by the input port default configuration (H5UDF=1,
PRELEN[1:0]=00):
SCI-PHY/Utopia 8-bit master:
SCI-PHY/Utopia 8-bit slave:
Any-PHY 8-bit slave:
53B
53B
54B (base cell + address)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
187
PMC [ PMC-SIERRA, INC ]
