RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x23: Microprocessor Insert FIFO Ready
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Unused
Unused
Unused
Unused
INSRDY
X
X
X
X
X
X
X
X
R
INSRDY
The INSRDY bit provides the ready status of the Microprocessor Insert FIFO.
A logic 1 in the INSRDY bit indicates that the Microprocessor Insert FIFO is
ready to accept a cell.
Note that the INSRDY bit will always return a logic 0 if the FIFO is currently
being written to.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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