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PM7350-PGI 参数 Datasheet PDF下载

PM7350-PGI图片预览
型号: PM7350-PGI
PDF下载: 下载PDF文件 查看货源
内容描述: [Support Circuit, 1-Func, CMOS, PBGA160, 15 X 15 MM, 1.81 MM HEIGHT, PLASTIC, BGA-160]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 245 页 / 898 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7350 S/UNI DUPLEX  
DATA SHEET  
PMC-1980581  
ISSUE 8  
DUAL SERIAL LINK PHY MULTIPLEXER  
Register 0x20: Microprocessor Cell Buffer Interrupt  
Bit  
Type  
Function  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
R
R
EXTCRCERRI  
EXTRDYI  
X
X
X
X
0
0
0
0
R
INSOVRI  
R
INSRDYI  
R/W  
R/W  
R/W  
R/W  
EXTCRCERRE  
EXTRDYE  
INSOVRE  
INSRDYE  
The Master Interrupt Enable bit of the Master Configuration register must also be  
logic 1 for the interrupt enables to take effect.  
INSRDYE:  
The INSRDYE bit allows the generation of an interrupt signal when the Insert  
FIFO becomes available. When INSRDYE is set to logic 1, the INTB output is  
asserted low when the INSRDYI bit is logic 1.  
INSOVRE:  
The INSOVRE bit controls the generation an interrupt signal when a write  
access is done to a full Insert FIFO. When INSOVRE is set to logic 1, the  
INTB output is asserted low when the INSOVRI bit is logic 1.  
EXTRDYE:  
The EXTRDYE bit allows the generation of an interrupt signal when an  
Extract FIFO becomes ready. When EXTRDYE is set to logic 1, the INTB  
output is asserted low when the EXTRDYI bit is logic 1.  
EXTCRCERRE:  
The EXTCRCERRE bit controls the generation an interrupt signal upon  
detection of a CRC-32 error at the end of a cell read access. When  
EXCRCERRE is set to logic 1, the INTB output is asserted low when the  
EXTCRCERRI bit is logic 1.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
121  
 
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