RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x12: Input Cell Available Enable (3rd)
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ICAEN[23]
ICAEN[22]
ICAEN[21]
ICAEN[20]
ICAEN[19]
ICAEN[18]
ICAEN[17]
ICAEN[16]
1
1
1
1
1
1
1
1
Register 0x13: Input Cell Available Enable (MSB)
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ICAEN[31]
ICAEN[30]
ICAEN[29]
ICAEN[28]
ICAEN[27]
ICAEN[26]
ICAEN[25]
ICAEN[24]
1
1
1
1
1
1
1
1
ICAEN[31:0]:
The four registers of ICAEN[31:0] control the polling of devices attached to
the SCI-PHY/Any-PHY input port.
When operating in master mode (IMASTER input set to logic 1), the
ICAEN[31:0] bits can be used to selectively remove a PHY device from the
polling sequence. Setting a bit of ICAEN[31:0] to logic 0 prevents the S/UNI-
DUPLEX to poll the corresponding device.
When operating in slave mode, the ICAEN[31:0] bits can be used to disable
logical channels. Logical channels are disabled in group of four consecutive
addresses, i.e. setting to logic 0 one or more bits of a four bit nibble of
ICA[31:0] disables all four corresponding logical channels. If a disabled PHY
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
112
PMC [ PMC-SIERRA, INC ]
