RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x0E: SCI-PHY/Any-PHY Input Interrupt Enables
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
X
X
X
X
X
0
Unused
Unused
Unused
R/W
R/W
R/W
PHYCELLE
CELLXFERRE
PARERRE
0
0
The Master Interrupt Enable bit of the Master Configuration register must also be
logic 1 for these enables to take effect.
PHYCELLE:
The PHYCELLE bit enables the generation of an interrupt when a physical
layer cell is transferred over the SCI-PHY/Any-PHY input port. When
PHYCELLE is set to logic 1, the interrupt is enabled. Physical layer cells are
defined in the I.361 standard as IDLE, unassigned and reserved cells (i.e.
cells with a VPI = 0 and VCI = 0). These cells should be filtered out by the
PHY device and would not normally be sent to the S/UNI-DUPLEX.
CELLXFERRE:
The CELLXFERRE bit enables the generation of an interrupt upon an invalid
start of cell sequence. When CELLXFERRE is set to logic 1, the interrupt is
enabled.
PARERRE:
The PARRERRE bit enables the generation of an interrupt on an input cell
parity error. When PARRERE is set to logic 1, the interrupt is enabled.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
109
PMC [ PMC-SIERRA, INC ]
