S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
The S/UNI-IMA-4 is primarily designed to be IMA v1.1 compliant. However, it may also be
programmed to analyze the incoming ICP cells and generate outgoing ICP cells using IMA v1.0
style, given the group is symmetrically configured. IMA v1.0 is not supported for asymmetrical
groups. Support of IMA V1.0 versus IMA v1.1 is selectable on a per-group basis.
Since the Rx link state is reported on the TX LID byte, the rx_link state is reported as unusable
prior to LID validation unlike in IMA 1.1 where it is reported as “Not in Group” prior to LID
validation.
10.2.9 SDRAM Interface
The S/UNI-IMA-4 uses the external SDRAM to buffer queued cells. The cell-buffer SDRAM
interface permits a single device, with 1M addressing capability, for a total of 16 Mbits of
storage. It has a 16-bit wide data bus, with CRC-16 checking applied on a per-cell basis. Each
cell takes up 64 bytes of memory. The CRC-16 is applied to words 0 through 30. If an error
occurs, an interrupt is sent to the microprocessor, and the cell is sent to the ATM layer anyway.
Note that a 64 Mbit or 256 Mbit SDRAM may also be used if 16 Mbit SDRAM is not available.
This will not increase the differential delay tolerance of the device beyond 1024 cells. The
hookup would be identical to the 16 Mbit hookup diagram.
The following diagram shows the cell storage map with the 64-byte memory boundary.
Figure 24 Cell Storage Map
Word #
15
Bits
0
Write Pointer + 0
1
DCB Status[15:0]
DCB Status[31:16]
2
3
4
5
Header1
Header3
Reserved
STATUS
Payload1
Header2
Header4
Reserved
Payload2
6
…
…
28
29
30
31
Payload45
Payload47
Reserved
CRC-16
Payload46
Payload48
The clock source drawn in the following diagrams must be completely skew aligned between
the S/UNI-IMA-4 and the SDRAM clock input pins.
The following diagram illustrates the configuration supported:
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
79
PMC [ PMC-SIERRA, INC ]
