S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
Figure 48 SDRAM Write Timing
SDRAM Write Mode Timing
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
sysclk
tRCD
act0 desel/nop
tRCD
act1 desel/nop
cbcmd
cbcsb
wr0
desel/nop
wr1
desel/nop
act2 desel/nop
cbrasb
cbcasb
cbweb
cbdqm
cbbs[1:0]
cba[11, 9:0]
cba[10]
even bank
odd bank
even bank
even row
even row
even co
prea
odd row
odd row
odd col
even row
even row
even col
prea
cbdq[31:0]
cba[11]
d0
even row
d1
d2
d3
d4
d5
d6
d7
d8
d9
d10 d11 d12 d13 d14 d15
d16
odd row
Figure 49 SDRAM Refresh
SDRAM Refresh Mode Timing
1
2
3
4
5
6
7
8
9
10
11
12
sysclk
tRC
desel/nop
cbcmd
cbcsb
refa
act
desel/nop
cbrasb
cbcasb
cbweb
cbdqm
cbbs[1:0]
cba[11:0]
cbdq[15:0]
00
400h
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
302
PMC [ PMC-SIERRA, INC ]
