Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
4.3.1 Processor Interface Signals
Table 8. Processor Interface Signals (38 Pins)
Drive/
Input Level
Slew
Rate
Signal Name
PCLK
Ball
Type
Description
Processor Clock
C6
In
CMOS
ADDRDATA(31:0)
B8, B7, D9, C8, D8,
E10, C10, E9, D10,
B10, C9, B9, C11,
E12, E11, E13, D11,
C12, D13, B11, B12,
D12, C13, B13, C14,
A13, B14, C15, D14,
E14, B15, E15
Bidir
5 ma/ 5 V or
LV TTL
Mod- Address/Data Bits 31 to 0 are part of the
erate 32-bit processor address/data bus.
(Mod)
/ADS
C7
E8
D7
In
In
5 V or LV
TTL
Address/Data Status is an active low sig-
nal that indicates an address state.
W_/RD
/READY
5 V or LV
TTL
Write_/Read is an active high signal that
selects a write cycle when it is high.
Out
5 ma
Mod Ready is an active low signal that indi-
cates the processor cycle is finished.
When this signal is deasserted, it is driven
high, then tristated.
/CS
A6
B6
In
5 V or LV
TTL
Chip Select is an active low signal that
selects the device for processor access.
/INTR
Out
5 ma
Mod Interrupt is an active low signal that indi-
cates an interrupt is present.
4.3.2 Statistics Interface Signal
Table 9. Statistics Interface Signal (1 Pin)
Drive/
Input Level
Slew
Rate
Signal Name Ball
STATS_STRB D6
Type
Description
Out
8 ma
Mod STATS_STRB is an active high signal that indicates a fixed
position in the cell time in the SYS_CLK domain. This can be
used to trigger external circuitry.
64
PMC [ PMC-SIERRA, INC ]
