Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
6.6 Miscellaneous Timing
Figure 65 shows the reset pin (/RESET) timing. The /RESET signal must be asserted for a mini-
mum time (Tres) to be registered properly in the presence of SE_CLK. The QRT remains in reset
while /RESET is asserted and starts performing normally after the first RX_CELL_START after
Trstproc. From then on RX_CELL_START must occur every 118 clocks. If an invalid
RX_CELL_START (that is, one that is not exactly 118 clocks after the preceding
RX_CELL_START) is received by the device (as occurs, for example, after a switchover), the
first RX_CELL_START is ignored and processing starts with the next RX_CELL_START.
Tres
/RESET(i)
Trstproc
SE_CLK(i)
RX_CELL_START(i)
Figure 65. Reset Timing
Symbol
Parameter
Signals
/RESET
/RESET
Min
Max
Unit
Tres
Trstproc
Reset assertion time.
Reset processing time.
40
SE_CLK periods
SE_CLK periods
60
96
PMC [ PMC-SIERRA, INC ]
