S/UNI®-JET Data Sheet
Released
Register 308H: SPLR Configuration
Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
Function
FORM[1]
FORM[0]
Reserved
Reserved
REFRAME
PLCPEN
Unused
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
X
0
R/W
EXT
EXT
The EXT bit disables the internal transmission system sublayer timeslot counter from
identifying DS1, DS3, E1, J2, E3 G.751, or E3 G.832 overhead bits. The EXT bit allows
transmission formats that are unsupported by the internal timeslot counter to be supported
using the ROHM[x] input. When a logic zero is written to EXT, input transmission system
overhead (for DS1, DS3, E1, J2, E3 G.751, and E3 G.832 formats) is indicated using the
internal timeslot counter. This counter is synchronized to the transmission system frame
alignment using the ROHM[x] (for DS1 or E1 ATM direct-mapped formats), or by the
integral framer block (for the DS3, J2, E3 G.751, or E3 G.832 formats).
When a logic one is written to EXT, indications on ROHM identify each transmission system
overhead bit.
PLCPEN
The PLCPEN bit enables PLCP framing. When a logic one is written to PLCPEN, PLCP
framing is enabled. The PLCP format is specified by the FORM[1:0] bits in this register.
When a logic zero is written to PLCPEN, PLCP related functions in the SPLR block are
disabled. PLCPEN must be programmed to logic zero for E3 G.832, J2, and arbitrary framing
formats.
REFRAME
The REFRAME bit is used to trigger reframing. When a logic one is written to REFRAME,
the S/UNI-JET is forced out of PLCP frame and a new search for frame alignment is initiated.
Note: Only a logic zero to logic one transition of the REFRAME bit triggers reframing;
multiple write operations are required to ensure such a transition.
Reserved
All Reserved bits must be set to logic zero for proper operation.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
98
PMC [ PMC-SIERRA, INC ]
