S/UNI®-JET Data Sheet
Released
Register 307H: S/UNI-JET Clock Activity Monitor and Interrupt Identification
Bit
Type
R
R
R
R
R
R
R
R
Function
INT
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
Unused
Unused
Unused
RCLKA
TICLKA
TFCLKA
RFCLKA
RFCLKA
The RFCLKA bit monitors for low-to-high transitions on the RFCLK input. RFCLKA is set
low when this register is read and is set high on a rising edge of RFCLK.
TFCLKA
The TFCLKA bit monitors for low-to-high transitions on the TFCLK input. TFCLKA is set
low when this register is read and is set high on a rising edge of TFCLK.
TICLKA
The TICLKA bit monitors for low-to-high transitions on the TICLK input. TICLKA is set
low when this register is read and is set high on a rising edge of TICLK.
RCLKA
The RCLKA bit monitors for low-to-high transitions on the RCLK input. RCLKA is set low
when this register is read and is set high on a rising edge of RCLK.
INT
When the INT bit is set to logic one, the S/UN-JET has generated the interrupt. The particular
block(s) the device that generated the interrupt can be identified by reading the S/UNI-JET
Interrupt Status Register. When the INT bit is set to logic zero, then the device has not
generated an interrupt. Note: The INT bit is valid only in register address 307H.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
97
PMC [ PMC-SIERRA, INC ]
