S/UNI®-JET Data Sheet
Released
Register 30AH: SPLR Interrupt Status
Bit
Type
Function
Unused
FEBEI
COLSSI
BIPEI
FEI
YELI
LOFI
OOFI
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
R
R
R
R
R
R
R
OOFI
The OOFI bit is set to logic one when a PLCP OOF defect is detected or removed. The OOF
defect state is contained in the SPLR Status Register. The OOFI bit position is set to logic
zero when this register is read.
LOFI
The LOFI bit is set to logic one when a PLCP LOF defect is detected or removed. The LOF
defect state is contained in the SPLR Status Register. The LOFI bit position is set to logic
zero when this register is read.
YELI
The YELI bit is set to logic one when a PLCP yellow alarm defect is detected or removed.
The yellow alarm defect state is contained in the SPLR Status Register. The YELI bit position
is set to logic zero when this register is read.
FEI
The FEI bit is set to logic one when a PLCP framing octet error is detected. A framing octet
error is generated when one or more errors are detected in the framing alignment octets (A1,
and A2), or the path overhead identification octets. The FEI bit position is set to logic zero
when this register is read.
BIPEI
The BIPEI bit is set to logic one when a PLCP bit interleaved parity (BIP) error is detected.
BIP errors are detected using the B1 byte in the PLCP path overhead. The BIPEI bit position
is set to logic zero when this register is read.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
102
PMC [ PMC-SIERRA, INC ]
