S/UNI®-JET Data Sheet
Released
Register 303H: S/UNI-JET Receive Configuration
Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
RFRM[1]
RFRM[0]
LOFINT[1]
LOFINT[0]
RSCLKR
RCLKINV
RPOSINV
RNEGINV
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
RNEGINV
The RNEGINV bit provides polarity control for input RNEG/RLCV/ROHM. When a logic
zero is written to RNEGINV, the input RNEG/RLCV/ROHM is not inverted. When a logic
one is written to RNEGINV, the input RNEG/RLCV/ROHM is inverted. The RNEGINV bit
setting does not affect the loopback data in diagnostic loopback.
RPOSINV
The RPOSINV bit provides polarity control for input RPOS/RDATI. When a logic zero is
written to RPOSINV , the input RPOS/RDATI is not inverted. When a logic one is written to
RPOSINV , the input RPOS/RDATI is inverted. The RPOSINV bit setting does not affect the
loopback data in diagnostic loopback.
RCLKINV
The RCLKINV bit provides polarity control for input RCLK. When a logic zero is written to
RCLKINV, RCLK is not inverted and inputs RPOS/RDATI and RNEG/RLCV/ROHM are
sampled on the rising edge of RCLK. When a logic one is written to RCLKINV, RCLK is
inverted and inputs RPOS/RDATI and RNEG/RLCV/ROHM are sampled on the falling edge
of RCLK.
RSCLKR
The RSCLKR bit is in effect only when the FRMRONLY bit in the S/UNI-JET Configuration
1 Register is set to logic one. When RSCLKR is a logic one, the RDATO, RFPO/RMFPO,
and ROVRHD outputs are updated on the rising edge of RSCLK. When RSCLKR is a logic
zero, the RDATO, RFPO/RMFPO, and ROVRHD outputs are updated on the falling edge of
RSCLK. If the RXGAPEN bit is a logic one, then RSCLKR affects RGAPCLK in the same
manner as it affects RSCLK.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
89
PMC [ PMC-SIERRA, INC ]
