S/UNI®-JET Data Sheet
Released
Register 301H: S/UNI-JET Configuration 2
Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
STATSEL[2]
STATSEL[1]
STATSEL[0]
TXMFPI
TXGAPEN
RXGAPEN
TXMFPO
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
RXMFPO
RXMFPO
The RXMFPO bit controls which of the outputs RMFPO or RFPO is valid. If RXMFPO is a
logic one, then RMFPO will be available. If RXMFPO is a logic zero, then RFPO will be
available. This bit is effective only if the FRMRONLY bit in the S/UNI-JET Configuration 1
Register is a logic one.
TXMFPO
The TXMFPO bit controls which of the outputs TMFPO[4:1] or TFPO[4:1] is valid. If
TXMFPO is a logic one, then TMFPO[4:1] will be available. If TXMFPO is a logic zero,
then TFPO[4:1] will be available. This bit is effective only if the FRMRONLY bit in the
S/UNI-JET Configuration 1 Register is a logic one. The TXGAPEN bit takes precedence over
the TXMFPO bit.
RXGAPEN
The RXGAPEN bit configures the S/UNI-JET to enable the RGAPCLK[x] outputs. When
RXGAPEN is a logic one, then the RGAPCLK[x] output is enabled. When RXGAPEN is a
logic zero, then the RSCLK[x] output is enabled. The FRMRONLY register bit must be a
logic one for RXGAPEN to have effect.
TXGAPEN
The TXGAPEN bit configures the S/UNI-JET to enable the TGAPCLK[x] outputs. When
TXGAPEN is a logic one, the TGAPCLK[x] output is enabled. When TXGAPEN is a logic
zero, then either the TFPO[x] or TMFPO[x] output is enabled, depending on the setting of the
TXMFPO register bit. The FRMRONLY register bit must be a logic one for TXGAPEN to
have effect.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
85
PMC [ PMC-SIERRA, INC ]
