S/UNI®-JET Data Sheet
Released
Figure 76 Microprocessor Interface Write Timing
A[10:0]
Valid Address
tS
tH
ALW
ALW
tV
L
tS
tH
LW
LW
ALE
tS
tV
tS
tH
AW
AW
WR
(CSB+W RB)
tH
DW
DW
D[7:0]
Valid Data
Notes
1. A valid write cycle is defined as a logical OR of the CSB and the WRB signals.
2. In non-multiplexed address/data bus architectures, ALE should be held high so parameters tS
,
ALW
tH
ALW
, tV , tS
, and tH
are not applicable.
is not applicable if address latching is used.
L
LW
LW
3. Parameter tH
AW
4. When a set-up time is specified between an input and a clock, the set-up time is the time in
nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
5. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds
from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
324
PMC [ PMC-SIERRA, INC ]
