S/UNI®-JET Data Sheet
Released
Notes
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal
to the 1.4 Volt point of the output.
2. Maximum output propagation delays are measured with a 100 pF load on the Microprocessor Interface
data bus, (D[7:0]).
3. A valid read cycle is defined as a logical OR of the CSB and the RDB signals.
4. In non-multiplexed address/data bus architectures, ALE should be held high so parameters tS
,
ALR
tH
, tV , tS , and tH
are not applicable.
ALR
L
LR LR
5. Parameter tH
AR
is not applicable if address latching is used.
6. When a set-up time is specified between an input and a clock, the set-up time is the time in
nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
7. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds
from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
Table 49 Microprocessor Interface Write Access (Figure 76)
Symbol
Parameter
Address to Valid Write Set-up Time
Min
10
Max
Units
ns
tS
tS
tS
AW
DW
ALW
Data to Valid Write Set-up Time
Address to Latch Set-up Time
Address to Latch Hold Time
Valid Latch Pulse Width
20
10
10
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
tH
ALW
L
tV
tS
Latch to Write Set-up
0
LW
tH
tH
tH
Latch to Write Hold
5
LW
DW
AW
WR
Data to Valid Write Hold Time
Address to Valid Write Hold Time
Valid Write Pulse Width
5
5
tV
40
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
323
PMC [ PMC-SIERRA, INC ]
