S/UNI®-JET Data Sheet
Released
Register 368H: RXCP-50 Idle Cell Header Mask
Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
MGFC[3]
MGFC[2]
MGFC[1]
MGFC[0]
MPTI[2]
MPTI[1]
MPTI[0]
MCLP
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
MGFC[3:0]
The MGFC[3:0] bits contain the mask pattern for the first, second, third, and fourth bits of the
first octet of the 53-octet cell. This mask is applied to the Idle Cell Header Pattern Register to
select the bits included in the cell filter. A logic one in any bit position enables the
corresponding bit in the pattern register to be compared. A logic zero causes the masking of
the corresponding bit.
MPTI[3:0]
The MPTI[3:0] bits contain the mask pattern for the fifth, sixth, and seventh bits of the fourth
octet of the 53-octet cell. This mask is applied to the Idle Cell Header Pattern Register to
select the bits included in the cell filter. A logic one in any bit position enables the
corresponding bit in the pattern register to be compared. A logic zero causes the masking of
the corresponding bit.
MCLP
The CLP bit contains the mask pattern for the eighth bit of the fourth octet of the 53-octet
cell. This mask is applied to the Idle Cell Header Pattern Register to select the bits included
in the cell filter. A logic one in this bit position enables the MCLP bit in the pattern register to
be compared. A logic zero causes the masking of the MCLP bit.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
204
PMC [ PMC-SIERRA, INC ]
