S/UNI®-JET Data Sheet
Released
Register 358H: TDPR Configuration
Bit
Type
R/W
R/W
R/W
Function
FLGSHARE
FIFOCLR
Reserved
Unused
EOM
ABT
CRC
EN
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
0
X
0
0
1
0
R/W
R/W
R/W
R/W
Consecutive writes to the TDPR Configuration, TDPR Interrupt Status/UDR Clear, and TDPR
Transmit Data Register and reads of the TDPR Interrupt Status/UDR Clear Register should not
occur at rates greater than 1/8th that of the clock selected by the LINESYSCLK bit of the S/UNI-
JET Miscellaneous Register (39BH).
EN
The EN bit enables the TDPR functions. When EN is set to logic one, the TDPR is enabled
and flag sequences are sent until data is written into the TDPR Transmit Data Register. When
the EN bit is set to logic zero, the TDPR is disabled and an all-ones Idle sequence is
transmitted on the datalink.
CRC
The CRC enable bit controls the generation of the CCITT_CRC frame check sequence (FCS).
Setting the CRC bit to logic one enables the CCITT-CRC generator and appends the 16-bit
FCS to the end of each message. When the CRC bit is set to logic zero, the FCS is not
appended to the end of the message. The CRC type used is the CCITT-CRC with generator
16
12
5
polynomial x + x + x + 1. The high order bit of the FCS word is transmitted first.
ABT
The Abort (ABT) bit controls the sending of the seven consecutive-ones HDLC abort code.
Setting the ABT bit to a logic one causes the 01111111 code (the 0 is transmitted first) to be
transmitted after the current byte from the TDPR FIFO is transmitted. The TDPR FIFO is
then reset. All data in the TDPR FIFO will be lost. Aborts are continuously sent and the FIFO
is held in reset until this bit is reset to a logic zero. At least one Abort sequence will be sent
when the ABT bit transitions from logic zero to logic one.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
183
PMC [ PMC-SIERRA, INC ]
