S/UNI®-JET Data Sheet
Released
Register 353H: RDLC Data
Bit
Type
R
R
R
R
R
R
R
R
Function
RD[7]
RD[6]
RD[5]
RD[4]
RD[3]
RD[2]
RD[1]
RD[0]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
Consecutive reads of the RDLC Status and Data Registers should not occur at rates greater than
1/10 that of the clock selected by the LINESYSCLK bit of the S/UNI-JET Miscellaneous
Register (39BH).
RD[7:0]
RD[7:0] contains the received data link information. RD[0] corresponds to the first received
bit of the data link message.
This register reads from the RDLC 128-byte FIFO buffer. If data is available, the FE bit in the
FIFO Input Status Register is logic zero.
When an overrun is detected, an interrupt is generated and the FIFO buffer is held cleared
until the RDLC Status Register is read.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
180