S/UNI®-JET Data Sheet
Released
Register 351H: RDLC Interrupt Control
Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
INTE
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
INTC[6]
INTC[5]
INTC[4]
INTC[3]
INTC[2]
INTC[1]
INTC[0]
INTC[6:0]
The INTC[6:0] bits control the assertion of FIFO fill level set point interrupts. The value of
INTC[6:0] = ‘b0000000 sets the interrupt FIFO fill level to 128.
INTE
The Interrupt Enable bit (INTE) must set to logic one to allow the internal interrupt status to
be propagated to the INTB output. When the INTE bit is logic zero the RDLC will not assert
INTB.
The contents of the Interrupt Control Register should only be changed when the EN bit in the
RDLC Configuration Register is logic zero. This prevents any erroneous interrupt generation.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
177
PMC [ PMC-SIERRA, INC ]
