S/UNI®-JET Data Sheet
Released
Register 338H: E3 FRMR Framing Options
Bit
Type
Unused
Function
X
Unused
Reserved
UNI
FORMAT[1]
FORMAT[0]
REFRDIS
REFR
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
REFR
A transition from logic zero to logic one in the REFR bit position forces the E3 Framer to
initiate a search for frame alignment. The bit must be cleared to logic zero, then set to logic
one again to initiate subsequent searches for frame alignment.
REFRDIS
The REFRDIS bit disables reframing under the consecutive framing bit error condition once
frame alignment has been found, leaving reframing to be initiated only by software via the
REFR bit. A logic one in the REFRDIS bit position causes the FRMR to remain "locked in
frame" once initial frame alignment has been found. A logic zero allows reframing to occur
when four consecutive framing patterns are received in error.
FORMAT[1:0]
The FORMAT[1:0] bits determine the framing mode used for pattern matching when finding
frame alignment and for generating the output status signals. The FORMAT[1:0] bits select
one of two framing formats. Refer to Table 16.
Table 16 E3 FRMR FORMAT[1:0] Configurations
FORMAT[1]
FORMAT[0]
Framing Format Selected
G.751 E3 format
G.832 E3 format
Reserved
0
0
1
1
0
1
0
1
Reserved
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
141
PMC [ PMC-SIERRA, INC ]
