S/UNI®-JET Data Sheet
Released
Register 335H: DS3 TRAN Diagnostic
Bit
Type
R/W
R/W
Function
DLOS
DLCV
Unused
DFERR
DMERR
DCPERR
DPERR
DFEBE
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
X
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
DFEBE
The DFEBE bit controls the insertion of FEBEs in the DS3 stream. When DFEBE is written
with a logic one, and the C-bit parity application is enabled, the three C-bits in M-subframe 4
are set to a logic zero. When DFEBE is written with a logic zero, FEBEs are indicated based
on receive framing bit errors and path parity errors.
DPERR
The DPERR bit controls the insertion of parity errors (P-bit errors) in the DS3 stream. When
DPERR is written with a logic one, the P-bits are inverted before insertion. When DPERR is
written with a logic zero, the parity is calculated and inserted normally.
DCPERR
The DCPERR bit controls the insertion of path parity errors in the DS3 stream. When
DCPERR is written with a logic one and the C-bit parity application is enabled, the three C-
bits in M-subframe 3 are inverted before insertion. When DCPERR is written with a logic
zero, the path parity is calculated and inserted normally.
DMERR
The DMERR bit controls the insertion of M-bit framing errors in the DS3 stream. When
DMERR is written with a logic one, the M-bits are inverted before insertion. When DMERR
is written with a logic zero, the M-bits are inserted normally.
DFERR
The DFERR bit controls the insertion of F-bit framing errors in the DS3 stream. When
DFERR is written with a logic one, the F-bits are inverted before insertion. When DFERR is
written with a logic zero, the F-bits are inserted normally.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
139
PMC [ PMC-SIERRA, INC ]
