PM7346 S/UNI-QJET
DATASHEET
PMC-960835
ISSUE 6
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Figure 11
- HCS Verification State Diagram
ATM DELINEATION
SYNC STATE
ALPHA
consecutive
incorrect HCS's
(To HUNT state)
No Errors
Detected
(Pass Cell)
Apparent Multi-Bit Error
(Drop Cell)
CORRECTION
MODE
Single Bit Error
(Correct error
and pass cell)
Drop Cell
DETECTION
MODE
DELTA
No Errors Detected in M
(M = 1, 2, 4, or 8) consecutive cells
(Pass Last Cell)
consecutive
correct HCS's
(From PRESYNC
state)
9.10 RXFF Receive FIFO
The Receive FIFO (RXFF) provides FIFO management and the S/UNI-QJET
receive cell interface. The receive FIFO contains four cells. The FIFO provides
the cell rate decoupling function between the transmission system physical layer
and the ATM layer.
In general, the management functions include filling the receive FIFO, indicating
when the receive FIFO contains cells, maintaining the receive FIFO read and
write pointers, and detecting FIFO overrun and underrun conditions.
The FIFO interface is “UTOPIA Level 2" compliant and accepts a read clock
(RFCLK) and read enable signal (RENB). The receive FIFO output bus
(RDAT[15:0]) is tri-stated when RENB is logic 1 or if the PHY device address
(RADR[4:0]) selected does not match this device's address. The interface
indicates the start of a cell (RSOC) and the receive cell available status (RCA
and DRCA[4:1]) when data is read from the receive FIFO (using the rising edges
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