PM7346 S/UNI-QJET
DATASHEET
PMC-960835
ISSUE 6
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
9.7 SPLR PLCP Layer Receiver
The PLCP Layer Receiver (SPLR) Block integrates circuitry to support DS1,
DS3, E1, and G.751 E3 PLCP frame processing. The SPLR provides framing for
PLCP based transmission formats.
The SPLR frames to DS1, DS3, E1, and G.751 E3 based PLCP frames with
maximum average reframe times of 635 µs, 22 µs, 483 µs, and 32 µs
respectively. Framing is declared (out of frame is removed) upon finding 2 valid,
consecutive sets of framing (A1 and A2) octets and 2 valid and sequential path
overhead identifier (POHID) octets. While framed, the A1, A2, and POHID octets
are examined. OOF is declared when an error is detected in both the A1 and A2
octets or when 2 consecutive POHID octets are found in error. LOF is declared
when an OOF state persists for more than 25 ms, 1 ms, 20 ms, or 1 ms for DS1,
DS3, E1, or G.751 E3 PLCP formats respectively. If the OOF events are
intermittent, the LOF counter is decremented at a rate 1/12 (DS3 PLCP), 1/10
(E1, DS1 PLCP) or 1/9(G.751 E3 PLCP) of the incrementing rate. LOF is thus
removed when an in-frame state persists for more than 250 ms for a DS1 signal,
12 ms for a DS3 signal, 200 ms for an E1 signal, or 9 ms for a G.751 E3 signal.
When LOF is declared, PLCP reframe is initiated.
When in frame, the SPLR extracts the path overhead octets and outputs them bit
serially on output RPOH, along with the RPOHCLK and RPOHFP outputs.
Framing octet errors and path overhead identifier octet errors are indicated as
frame errors. Bit interleaved parity errors and far end block errors are indicated.
The yellow signal bit is extracted and accumulated to indicate yellow alarms.
Yellow alarm is declared when 10 consecutive yellow signal bits are set to logical
1; it is removed when 10 consecutive received yellow signal bits are set to logical
0. The C1 octet is examined to maintain nibble alignment with the incoming
transmission system sublayer bit stream.
9.8 ATMF ATM Cell Delineator
The ATM Cell Delineator (ATMF) Block integrates circuitry to support HCS-based
cell delineation for non-PLCP based transmission formats. The ATMF block
accepts a bit serial cell stream from an upstream transmission system sublayer
entity (such as the T3-FRMR, E3-FRMR, or J2-FRMR Block) and performs cell
delineation to locate the cell boundaries. For PLCP applications, ATM cell
positions are fixed relative to the PLCP frame, but the ATMF still performs cell
delineation to locate the cell boundaries.
Cell delineation is the process of framing to ATM cell boundaries using the
header check sequence (HCS) field found in the ATM cell header. The HCS is a
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