PM7346 S/UNI-QJET
DATASHEET
PMC-960835
ISSUE 6
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
More precisely, filtering is performed when filtering is enabled or when HCS
errors are found when HCS checking is enabled. Otherwise, all cells are passed
on regardless of any error conditions. Cells can be blocked if the HCS pattern is
invalid or if the filtering 'Match Pattern' and 'Match Mask' registers are
programmed with a certain blocking pattern. ATM Idle cells are filtered by
default. For ATM cells, Null cells (Idle cells) are identified by the standardized
header pattern of 'H00, 'H00, 'H00 and 'H01 in the first 4 octets followed by the
valid HCS octet.
While the cell delineation state machine is in the SYNC state, the HCS
verification circuit implements the state machine shown in Figure 11.
In normal operation, the HCS verification state machine remains in the
'Correction' state. Incoming cells containing no HCS errors are passed to the
receive FIFO. Incoming single-bit errors are corrected, and the resulting cell is
passed to the FIFO. Upon detection of a single-bit error or a multi-bit error, the
state machine transitions to the 'Detection' state.
A programmable hysteresis is provided when dropping cells based on HCS
errors. When a cell with an HCS error is detected, the RXCP-50 can be
programmed to continue to discard cells until m (where m = 1, 2, 4, 8) cells are
received with a correct HCS. The mth cell is not discarded (see Figure 11). Note
that the dropping of cells due to HCS errors only occurs while the ATMF is in the
SYNC state.
Cell delineation can optionally be disabled, allowing the RXCP-50 to pass all
data bytes it receives.
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