PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
5
BLOCK DIAGRAM
Figure 4
- Normal Operating Mode
TSOC
Bit
JTAG Test
HDLC
TDAT[7:0]
Oriented
Access Port
Transmitter
Code
TXPRTY
Transmitter
TCA[4:1]
TCAMPH/TWRENB[4]
TWA[1]/TWRENB[3]
TWA[0]/TWRENB[2]
TWRMPHB /TWRENB[1]
TFCLK
Inband
Loopback
Code
Digital
TCLKO[4:1]
TDP/TDD[4:1]
TDN/TOHO[4:1]
Pulse
Density
Enforcer
T1/E1
Tx ATM
4 Cell
FIFO
Transmit
Interface
Tx ATM Cell
Processor
Framing
Insertion
Generator
Multi-
PHY
I/F
RSOC
Digital
Receive
Interface
Rx ATM
4 Cell
RDAT[7:0]
RCLKI[4:1]
T1/E1
Rx ATM Cell
Processor
RDP/RDD[4:1]
RXPRTY
Framer
FIFO
RCA[4:1]
RDN/RLCV/
ROH[4:1]
RCAMPH/RRDENB[4]
RRA[1]/RRDENB[3]
RRA[0]/RRDENB[2]
RRDMPHB /RRDENB[1]
RFCLK
Pulse
Bit
Inband
Code
Performance
Monitor
Alarms
Density
Violation
Detector
HDLC
Oriented
Code
Microprocessor I/F
Integrator
Receiver
Detector
Receiver
Figure 5
- Loopback Modes
Bit
JTAG Test
HDLC
Oriented
Code
Access Port
Transmitter
Transmitter
Inband
T1/E1
Framing
Insertion
Pulse
Density
Enforcer
Digital
Tx ATM
4 Cell
FIFO
Loopback
Code
Tx ATM Cell
Processor
Transmit
Interface
Generator
Multi-
LINE
LOOPBACK
DIAGNOSTIC
LOOPBACK
PAYLOAD
LOOPBACK
PHY
I/F
Rx ATM
4 Cell
Digital
T1/E1
Rx ATM Cell
Processor
Receive
Framer
FIFO
Interface
Pulse
Bit
Inband
Performance
Monitor
Alarms
Density
Violation
Detector
HDLC
Oriented
Code
Code
Microprocessor I/F
Integrator
Receiver
Detector
Receiver
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
14
PMC [ PMC-SIERRA, INC ]
