PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
For both T1 and E1 configurations, the S/UNI-MPH interprets the received frame
alignment and extracts the transmission format payload which carries the
received ATM cell payload.
The S/UNI-MPH frames to the ATM payload using cell delineation. HCS error
correction is optionally provided. Idle/unassigned cells may be dropped
according to a programmable filter. Cells are also dropped upon detection of an
uncorrectable header check sequence error. The ATM cell payloads are
descrambled.
Valid, assigned cells are written to a four cell FIFO buffer. These cells are read
from the FIFO using a synchronous 8 bit wide datapath interface with a cell-
based handshake. Counts of received ATM cell headers that are errored and
uncorrectable, those that are errored and correctable and all passed cells are
accumulated independently for performance monitoring purposes. A multi-PHY
interface allows the four receive FIFOs (one for each T1 or E1 port) to be
serviced via a single 8 bit wide bus.
On the transmit side, when configured for T1 processing, the S/UNI-MPH
generates framing for SF and ESF DS1 formats. The S/UNI-MPH can also
generate in-band loopback codes, ESF bit oriented codes, and transmit HDLC
messages on the ESF data link.
On the transmit side, when configured for E1 processing, the S/UNI-MPH
generates framing for a basic G.704 2048 kbit/s signal. The signalling multiframe
alignment signal may be optionally inserted and the CRC multiframe structure
may be optionally inserted. HDLC messages on a data link can be transmitted.
The data link may be inserted into timeslot 16 or may be inserted into the
national bits.
For both T1 and E1 configurations, the S/UNI-MPH generates the transmitted
frame and inserts the transmit ATM cell payload into the transmission format
payload appropriately.
ATM cells are written to an internal programmable-length 4-cell FIFO using a
synchronous 8 bit wide datapath interface. Idle/unassigned cells are
automatically inserted when the internal FIFO contains less than one cell. The
S/UNI-MPH generates of the header check sequence and scrambles the payload
of the ATM cells. Each of these transmit ATM cell processing functions can be
enabled or bypassed. A multi-PHY interface allows the four transmit FIFOs
(one for each T1 or E1 port) to be serviced via a single 8 bit wide bus.
The S/UNI-MPH is configured, controlled and monitored via a generic 8-bit
microprocessor bus interface. The S/UNI-MPH also provides a standard 5 signal
P1149.1 JTAG test port for boundary scan board test purposes.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
16
PMC [ PMC-SIERRA, INC ]
