PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
Figure 2
Signals
- Example 2. DS3 Port Carrying Multiplexed T1 or E1 ATM UNI
1.544 MHz
6.312 MHz
44.736 MHz
Transmit
Transmit
Optional Transmit
Reference Clock
Reference Clock
Reference Clock
# 1
DSX-3
Line Interface With
Clock Recovery
DSX-3
Analog
Interface
PM7344
S/UNI-MPH
PM8313
D3MX
Quad T1/E1
Multi-PHY
Integrated M13
Multiplexer
User Network Interface
12.352 MHz
1.544 MHz
# 7
PM7344
S/UNI-MPH
Quad T1/E1
Multi-PHY
SCI-PHYTM
Multi-PHY
User Network Interface
ATM Cell Bus
Generic
Crystal Oscillator Clock
12.352 MHz
Microprocessor
Bus
Example 2 shows seven PM7344 S/UNI-MPH devices used with a PM8313
D3MX device and a generic DSX-3 LIU device being used to implement a DS3
port where the DS3 carries a multiplex of DS1 (or E1) UNI signals.
In this example, each S/UNI-MPH provides four duplex DS1 signals to the D3MX
device which, in turn, performs the asynchronous multiplex and demultiplex
function required to map these into a DS3 signal. The D3MX may use the
traditional M23 format or may use the C-bit parity format when performing this
multiplex. Note that the D3MX may also be configured for G.747 multiplexing of
three E1 signals into each of the seven DS2 signals within the overall DS3
signal. Many generic DSX-3 line interface unit devices may be used with the
D3MX to implement a DSX-3 electrical interface on the high speed line side of
such a system. Each S/UNI-MPH device implements the T1 or E1 UNI function
for four T1 or E1 streams. The seven S/UNI-MPH devices may be serviced by a
common ATM layer device through a shared (SCI-PHYTM) multi-PHY bus.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
11
PMC [ PMC-SIERRA, INC ]
