PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
Figure 26
- Typical Data Frame
TRANSMIT
RECEIVE
BIT: 8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
0
FLAG
Address (high)
(low)
data bytes written to the
Transmit Data Register
and serially transmitted,
bit 1 first
data bytes received and
transferred to the FIFO,
bit 1 first
CONTROL
Frame Check
Sequence (FCS)
appended after EOM
is set, if CRC is set
0
1
1
1
1
1
1
0
FLAG
Bit 1 is the first serial bit to be transmitted or received.
Both the address and control bytes must be supplied by an external processor
and are shown for reference purposes only.
Key used on subsequent diagrams:
Flag
- flag sequence (01111110)
- abort sequence (01111111)
- n frame data bytes
Abort
D1 - Dn
R
- remainder bits (less than 8)
- CRC-CCITT information
- groupings of 8 bits
C1, C2
B1, B2, B3
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
235
PMC [ PMC-SIERRA, INC ]
