PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
Figure 29
- XFDL Normal Data Sequence
Serial Data
inserted into
ESF FDL
CRC1 CRC2
Flag D1
D2
Dn
Flag D1
TDLINT[x]
D[7:0]
INTE D1 D2
D3
D4
EOM
INTE
INTE D1
D2
D3
This diagram shows the relationship between XFDL inputs and outputs for the
case where interrupts and CRC are enabled for regular data transmission. The
process is started by setting the INTE bit in the Configuration/Control Register to
logic 1, thus enabling the TDLINT[x] signal. When TDLINT[x] goes high, the
interrupt service routine is started, which writes the first byte (D1) of the data
frame to the Transmit Data Register. When this byte begins to be shifted out on
the data link, TDLINT[x] goes high. This restarts the interrupt service routine,
and the next data byte (D2) is written to the Transmit Data Register. When D2
begins to be shifted out on the data link, TDLINT[x] goes high again. This cycle
continues until the last data byte (Dn) of the frame is written to the Transmit Data
Register. When Dn begins to be shifted out on the data link, TDLINT[x] again
goes high. Since all the data has been sent, the interrupt service routine sets the
EOM bit in the Configuration/Control Register to logic 1. The TDLINT[x] interrupt
should also be disabled at this time by setting the INTE bit to logic 0. The XFDL
will then shift out the two-byte CRC word and closing flag, which ends the frame.
Whenever new data is ready, the TDLINT[x] signal can be re-enabled by setting
the INTE bit in the Configuration/Control Register to logic 1, and the cycle starts
again.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
238
PMC [ PMC-SIERRA, INC ]
