PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
Figure 27
- RFDL Normal Data and Abort Sequence
B1 B2 B3
B1
Serial Data
extracted from
ESF FDL
Flag D1 D2 D3
Dn-1 Dn
Flag
Abort
D1 R
R
C1 C2
RDLINT[x]
RDLEOM[x]
D[7:0]
Dn-1
Dn-3 Dn-2
D1 D2
Dn B1 B2 B3
EOM
D1 B1
ABORT
EOM
This diagram shows the relationship between RFDL inputs and outputs for the
case where interrupts are programmed to occur when one byte is present in the
FIFO buffer. The RFDL is assumed to be operating in the interrupt driven mode.
Each read shown is composed of two register reads: first a read of the Data
Register, followed by a read of the Status Register. A read of the Data Register
sets the RDLINT[x] output to low if no more data exists in the FIFO buffer. The
status of the FE bit returned in the Status Register read will indicate the FIFO
buffer fill status as well. The Data Register read Dn-2 is shown to occur after two
bytes have been written into the buffer. The RDLINT[x] output does not go low
after the first Data Register read because a data byte still remains to be read.
The RDLINT[x] output goes low after Data Register read Dn-1. The FE bit will be
logic 0 in Status Register read Dn-2 and logic 1 in Status Register read Dn-1.
The RDLEOM[x] output goes high as soon as the last byte in the frame is read
from the Data Register. The RDLINT[x] output will go low if the FIFO buffer is
empty. The next Status Register read will return a value of logic 1 for the EOMR
and FLG bits, and cause the RDLEOM[x] output of the RFDL to return low.
In the next frame, the first data byte is received, and after a delay of ten bit
periods, it is written to the FIFO buffer, and read by the processor after the
interrupt. When the abort sequence is detected, the data received up to the
abort is written to the FIFO buffer and an interrupt generated. The processor
then reads the partial byte from the Data Register and the RDLEOM[x] output is
set high. The processor then reads the Status Register which will return a value
of logic 1 for the EOMR and FLG bits, and set the RDLEOM[x] output low. The
FIFO buffer is not cleared when an abort is detected. All bytes received up to the
abort are available to be read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
236
PMC [ PMC-SIERRA, INC ]
