PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
12
OPERATION
12.1 Hardware Configuration
The S/UNI-IMA-8 is powered up with the line interface disabled.
The Any-PHY/UTOPIA interface can be set up in different modes. The Any-
PHY/UTOPIA interface will remain tri-state until configured and the respective
RA_ENABLE/TA_ENABLE bits are set.
12.2 Start-Up
The S/UNI-IMA-8 uses an internal DLL on SYSCLK to maintain low skew on the
ram interface. When the chip is taken out of hardware reset, the DLL will go into
hunt mode and will adjust the internal SYSCLK until it aligns with the external
SYSCLK. The microprocessor should poll the RUN bit in DLL CONTROL
STATUS register until this bit is set.
At this point the entire chip with the exception of the microprocessor interface
and the DLL are in reset. Before any configuration can be done, including
accessing the ram, the chip must be taken out of software reset by clearing the
SW_RESET bit in the Global Reset Register. Once taken out of reset, the
internal ram reset procedure is automatically initiated. The microprocessor
should poll the BIST_DONE bit in the Global Reset register to determine when
the internal RAM reset is complete. While the internal ram is initializing, access
to all internal rams are prohibited, accesses attempted during this period of time
are ignored.
Once the chip is taken out of reset, the external SDRAM should be cleared to all
zeros to ensure no false CRC errors are reported. Access to the SDRAM is
through the SDRAM Diagnostic access port as discribed in 12.6.1. At this point,
the Any-PHY/UTOPIA interface is disabled and all Any-PHY/UTOPIA outputs are
tri-stated. Also, the line side interfaces are disabled and all internal registers are
in their reset state.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
258
PMC [ PMC-SIERRA, INC ]
