PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
Register 0x140- 0x14E: RCAS Link #0 to Link #7 Configuration
Bit
Type
Function
Default
15:3
R
Unused
Reserved
E1
X
0
0
0
2
1
0
R/W
R/W
R/W
CEN
This register configures operational modes of receive link #0 to link #7
(RSDATA[N]/ RSCLK[N] where 0 ≤ N ≤ 7).
CEN:
The channelize enable bit (CEN) configures link #N for channelized operation.
RSCLK[N] is held low during the T1 framing bit and during the E1 framing
byte. The data bit on RSDATA[N] that is clocked in by the first rising edge of
RSCLK[N] after an extended low period is considered to be the most
significant bit of time-slot 1. When CEN is set low, link #N is unchannelized.
The E1 register bit is ignored. RSCLK[N] is gapped during non-data bytes. All
data bits are treated as a contiguous stream with arbitrary byte alignment.
E1:
The E1 frame structure select bit (E1) configures link #N for channelized E1
operation when CEN is set high. RSCLK[N] is held low during the FAS and
NFAS framing bytes. The data bit on RSDATA[N] that is associated with the
first rising edge of RSCLK[N] after an extended low period is considered to be
the most significant bit of time-slot 1. Link data is present at time-slots 1 to 31.
When E1 is set low and CEN is set high, link #N is configured for channelized
T1 operation. RSCLK[N] is held low during the framing bit. The data bit on
RSDATA[N] that is associated with the first rising edge of RSCLK[N] after an
extended low period is considered to be the most significant bit of time-slot 1.
Link data is present at time-slots 1 to 24. E1 is ignored when CEN is set low.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
141
PMC [ PMC-SIERRA, INC ]
