PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
Register 0x180: TCAS Indirect Link and Time-slot Select
Bit
Type
Function
Default
15
14
13:11
10:8
7:5
RO
R/W
Busy
RWB
Unused
LINK[2:0]
Unused
TSLOT[4:0]
X
0
X
0
X
0
R/W
R/W
4:0
This register provides the link number and time-slot number used to access the
timeslot provision RAM. Writing to this register triggers an indirect register access
and transfers the contents of the Indirect Link Data register to an internal holding
register.
TSLOT[4:0]
The indirect time-slot number bits (TSLOT[4:0]) indicate the time-slot to be
configured or interrogated in the indirect access. For a channelized T1 link,
time-slots 1 to 24 are valid. For a channelized E1 link, time-slots 1 to 31 are
valid. For unchannelized links, only time-slot 0 is valid.
LINK[2:0]
The indirect link number bits (LINK[2:0]) select amongst the 8 transmit links to
be either configured or interrogated in the indirect access.
RWB
The indirect access control bit (RWB) selects between a configure (write) or
interrogate (read) access to the timeslot provision RAM. The address to the
timeslot provision RAM is constructed by concatenating the TSLOT[4:0] and
LINK[4:0] bits. Writing a logic zero to RWB triggers an indirect write operation.
Data to be written is taken from the PROV and the VLINK[2:0] bits of the
Indirect Data register. Writing a logic one to RWB triggers an indirect read
operation. Addressing of the RAM is the same as in an indirect write
operation. The data read can be found in the PROV and the VLINK[2:0] bits of
the Indirect Link Data register after the BUSY bit has cleared.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
142
PMC [ PMC-SIERRA, INC ]
