PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
Register 0x012: Miscellaneous Interrupt Enable Register
Bit
Type
Function
Default
15:5
4
RO
R/W
Unused
TC_INTR_FOVR_ER
R_EN
0
0
3
2
1
0
R/W
R/W
R/W
R/W
SDRAM_CRC_ERR_
EN
TX_UTOP_CELLXFE
RR_EN
TX_UTOP_PAR_ERR 0
EN
RX_UTOP_XFR_ERR 0
_EN
0
0
The above enable-bits control the corresponding interrupt bits in the
Miscellaneous Interrupt register. When an enable-bit is set to a logic 1, the
corresponding error event will cause the MISC_INT bit to be set in the Master
Interrupt Register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
109
PMC [ PMC-SIERRA, INC ]
