PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
Register 0x010: Master Interrupt Enable Register
Bit
Type
Function
Default
15:5
8
7
6:4
3
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
0
0
0
0
0
0
0
0
TC_INTR_EN
MISC_INTR_EN
Reserved
ICP_CELL_AVL_EN
RDAT_INTR_EN
TIMA_INTR_EN
RIPP_INTR_EN
1
0
The above enable-bits control the corresponding interrupt bits in the Master
Interrupt Register. When an enable-bit is set to a logic 1, the corresponding error
event will cause INTB to go active.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
108