PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
required for correct operation of IMA. Failure to perserve the cells will lead to
increased numbers of OIF violations and data misordering. Header correction is
not implemented.
For IMA operation, there are two unique features: the first is optionally passing
cells with errored HEC; the second results in passing cells during OCD and LCD.
This is to enable the IMA to perform a fast recovery from error conditions. An
OCD event will result in a loss of IMA frame sync to ensure differential delay
checking is performed.
10.5 Line Side Physical Layer
10.5.1 TX Clock/Data (TCAS)
The S/UNI-IMA-8 supports up to eight 2-pin Clock/Data serial interfaces to
interface with standard framers. Each link is independent and has its own
associated clock. To enable easier support of CTC, a common clock is also
supported using the CTSCLK pin. The S/UNI-IMA-8 responds to the active edge
of each transmit clock by generating a single bit.
When the external framer needs to insert transmission overhead (such as
framing bits) into the data stream provided by the S/UNI-IMA-8, the framer is
required to gap the transmit clock provided to the S/UNI-IMA-8. This will prevent
the S/UNI-IMA-8 from outputting data bits during the overhead bit period(s).
The Transmit Channel Assigner block (TCAS) processes up to eight virtual links.
Data for all links is sourced from a single byte-serial stream from the TC layer.
For each link, the TCAS provides a holding register. The TCAS also performs
parallel-to-serial conversion to form a bit-serial stream. When multiple links are in
need of data, TCAS requests data from upstream blocks on a fixed priority basis
with link TSDATA[0] having the highest priority and link TSDATA[7] the lowest.
Links containing a T1 or an E1 stream may be channelized. Data at each time-
slot may be assigned either: (1) to be sourced from the virtual link or (2) to be
unassigned. This mechanism of assigning timeslots enables support of fractional
links. The link clock should only be active during time-slots 1 to 24 of a T1 stream
and inactive during the frame bit. Similarly, the clock is only active during time-
slots 1 to 31 of an E1 stream and inactive during the framing byte. The first bit of
time-slot 1 of a channelized link is identified by noting the absence of the clock
and its re-activation. With knowledge of the transmit link and time-slot identity, the
TCAS performs a table look-up to identify which timeslots are in use.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
87
PMC [ PMC-SIERRA, INC ]
