PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
Figure 21
- 2 MByte
clock source
1
SYSCLK
CBCSB
CBRASB
CBCASB
CBWEB
CKE
CLK
Addr/Ctrl
CBBS[0]
CBA[11:0]
2 x 2k x 256 x 16
CBDQM
DQM
CBDQ[15:0]
DQ[15:0]
Figure 22
- 8 MByte
clock source
1
SYSCLK
CKE
CBCSB
CBRASB
CBCASB
CBWEB
CLK
Addr/Ctrl
CBBS[1:0]
CBA[11:0]
4 x 4k x 256 x 16
DQM
CBDQM
CBDQ[15:0]
DQ[15:0]
There are three processes, all of which are arbitrated by the SDRAM arbiter, that
access the cell buffer SDRAM:
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
83