PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
ICP_CELL_AVL indicates that an ICP cell is available in the ICP cell buffer. To
enable diagnostics, the capability to forward a group’s ICP cells to the
microprocessor is provided. When a cell is forwarded to the microprocessor, it is
placed in the ICP cell buffer and the interrupt is triggered. As new ICP cells
arrive, they overwrite the ICP cell buffer unless the buffer is locked for reading.
Once the ICP cell buffer is locked, further ICP cells will not be forwarded until the
ICP cell buffer is unlocked. This trace can be enabled on a per-group basis.
10.6.2.3
Miscellaneous Interrupts
MISC_INTR indicates that an interrupt condition exists in the Miscellaneous
Interrupt register. These bits are read-and-clear and usually indicate that
transitory conditions have occurred, such as parity errors, SDRAM CRC errors,
interrupt FIFO overflows, and UTOPIA L2 interface errors.
10.6.3 Registers
The Register Memory Map in Table 5 shows where the normal mode registers
are accessed. The resulting register organization is split into sections: Master
configuration registers, TC Layer, Clock/Data Interface and IMA Sublayer
registers.
On power up, the S/UNI-IMA-8 requires configuration. For proper operation,
register configuration is necessary in order to program addresses for the Any-
PHY ports, enable the SDRAM, configure the Line interface and chose IMA or
TC mode for each link/group. By default, interrupts will not be enabled.
The Line-side-access defaults to a disabled state; this results in all line side
output pins being tristated. When the line mode is chosen, Clock/Data, the pins
will be enabled.
Table 5 Register Memory Map
Address
Register
0x000 –
0x05E
Master Configuration and Interrupts
0x000
0x002
0x004
Global Reset
Global Configuration
JTAG ID (MSB)
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91
PMC [ PMC-SIERRA, INC ]
