PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
The details of the differences between IMA v1.1 and IMA v1.0 can be found in
appendix C of the ATM Forum IMA 1.1 specification.
The S/UNI-IMA-8 is primarily designed to be IMA v1.1 compliant. However, it may
also be programmed to analyze the incoming ICP cells and generate outgoing
ICP cells using IMA v1.0 style, given the group is symmetrically configured. IMA
v1.0 is not supported for asymmetrical groups. Support of IMA V1.0 versus IMA
v1.1 is selectable on a per-group basis.
Since the rx link state is reported on the TX LID byte, the rx_link state is reported
as unusable prior to LID validation unlike in IMA 1.1 where it is reported as “Not
in Group” prior to LID validation.
10.2.9 SDRAM Interface
The S/UNI-IMA-8 uses the external SDRAM to buffer queued cells. The cell-
buffer SDRAM interface permits a single device, with 4M addressing capability,
for a total of 8 Mbytes of storage. It has a 16-bit wide data bus, with CRC-16
checking applied on a per-cell basis. Each cell takes up 64 bytes of memory. The
CRC-16 is applied to words 0 through 30. If an error occurs, an interrupt is sent
to the microprocessor, and the cell is sent to the ATM layer anyway.
The following diagram shows the cell storage map with the 64-byte memory
boundary.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
81
PMC [ PMC-SIERRA, INC ]
