S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
In the event the PHY queue for which the cell at the head of the FIFO is destined becomes
inoperative (i.e. no cells are accepted for that PHY), that cell must be dealt with so that it does not
prevent other PHY devices from having cells inserted in the cell stream. The Cell Processor can
be programmed with a Head-of-Line Time Out function to deal with this problem. If a PHY
queue does not make room available within a specified time, the S/UNI-ATLAS-3200 can take a
programmable action on that cell. The time out counter is defined in terms of cell periods at the
SYSCLK rate, where one cell period is equal to 22 clock cycles. The Head-of-Line Time Out can
be programmed to take into account the worst case time for cell transmission (e.g. 48 cell periods,
plus 2-3 cell periods for robustness, at an STS-1 rate). The S/UNI-ATLAS-3200 may be
programmed to discard the cell, or to route the cell to the Microprocessor Interface, where it may
be stored and re-inserted at a later time when the PHY problem has been resolved. This function
is provided solely to retain a quality of service for other PHY devices in case a catastrophic event
occurs on a particular PHY queue. In normal operating mode, this situation will never be
encountered. The Head-of-Line Time Out can optionally be disabled.
Cells from the IBCIF are, by default, header-translated much like cells from the Input Cell
Interface. For routing and processing, they are treated as cells that were not received, but
(potentially) are transmitted. Thus, they are never included in terminated or monitored PM flows,
OAM cells are not dropped at flow end points, and AIS, CC, and RDI alarms are not affected.
Cells from the IBCIF are, however, subject to counting and/or policing if their cell type (usually
OAM cells) are configured to be counted and/or policed. Cells from the BCIF may optionally not
be translated (if the Xlate_From_IBCIF register bit is logic 0) or may have the Prepend/Postpend
2 word from the VC Record Table inserted onto the Prepend/Postpend 1 or HEC/UDF words (via
the IBCIF_P2_To_P1 and IBCIF_P2_To_HECUDF bits). These bits are useful when using the
BCIFs in a non-standard way, and reside in the Cell Processor Routing Configuration register.
10.17.3 Internal DRAM Access
Microprocessor access to the internal DRAM is provided to allow access to the VC Table records.
The access registers allow the microprocessor to read or write an entire VC Table record in one
operation. The Cell Counts, Alternate Cell Counts, and Non-Compliant Counts each have a Clear
On Read register bit that allows the corresponding count to be cleared whenever a read is
performed. Each field in the VC table is individually maskable during writes, to permit settings
to be changed without affecting the operation of the device.
The VC Table records are protected by a CRC-10 calculated over the entire entry. This CRC is
automatically generated by S/UNI-ATLAS-3200 during microprocessor write operations and
normal processing, and is automatically checked during reads, including microprocessor reads, of
the DRAM.
Internal DRAM access bandwidth is shared between the internal processing cell processing
operations and microprocessor accesses. The microprocessor is guaranteed enough bandwidth to
perform at least 140,000 DRAM accesses per second. This is enough to support over 8000
connection setups/teardowns and allow a read or write the VC table record for all 64K VCs.
Additional microprocessor access to the DRAM may consume bandwidth required to send OAM-
FM and OAM-PM cells and to do background processes, if the aggregate (user cells + generated
OAM cells) is in excess of OC-48.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
139
PMC [ PMC-SIERRA, INC ]
