RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
CRL_CLK
Input
D18
Common Receive Line Clock is a
receive line clock which can be shared
across all lines. Whether this clock is
used or not for a given line is
dependent on the value of
CLK_SOURCE_RX in the
LIN_STR_MODE memory register for
that line.
When the MVIP_EN bit is set in
LS_Ln_CFG_REG then this is the C4B
input; the common 4.096 MHz clock.
Line Interface Signals(H-MVIP)(13)
Pin Name
Type
Pin No.
Function
LINE_MODE
Input
B18
Determines the mode of operation for the
line interface:
0)Direct Mode
1)H-MVIP Mode
F0B
Input
V19
Frame Sync 0 is the active low frame
synchronization input signal used to
indicate the start of a frame.
TL_DATA[1]
TL_DATA[0]
Output U19
V20
Transmit Line Serial Data 1 to 0 carry the
received data to the corresponding framer
devices. or an H_MVIP backplane.
Maximum output current (IMAX) = 6 mA.
TL_SIG[1]
TL_SIG[0]
Output R20
Y22
Transmit Line Signal 1 to 0 are the CAS
signaling outputs to the corresponding
framer devices in SDF-MF mode. H-MVIP
does not support signaling directly, but
these signals can be used to transport
signaling if needed.
Maximum output current (IMAX) = 6 mA
C16B
Input
C16
Clock 16 MHz is the clock used to transfer
data across the H-MVIP bus. The clock
runs twice as fast as the data rate. This
common clock is used in both the receive
and transmit direction.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
54
PMC [ PMC-SIERRA, INC ]
