RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
TL_CLK[7]/TSM[7]
I/O
A20
C21
E19
H22
K22
N21
R22
U21
Transmit Line Channel Clock 7 to 0 are
the clock lines for the sixteen lines.
They clock the data from the
AAL1gator-8 to the corresponding
framer devices.
TL_CLK[6]/TSM[6]
TL_CLK[5]/TSM[5]
TL_CLK[4]/TSM[4]
TL_CLK[3]/TSM[3]
TL_CLK[2]/TSM[2]
TL_CLK[1]/TSM[1]
TL_CLK[0]/TSM[0]
Depending on the value of the
TL_CLK_OE pin and the
CLK_SOURCE_TX field in the
LIN_STR_MODE memory register,
these pins are either outputs or inputs.
If TLCLK_OUTPUT_EN is high, these
pins are outputs and the clock is
sourced internally at power up. This
can later be changed by the
CLK_SOURCE_TX field.
Note that if CLK_SOURCE_TX /=
“000” then this pin is an output, even if
it is not driving a clock. A clock will
only be driven if in E1 or T1 mode and
either the internal clock synthesizer is
being used or the clock is being
looped. CLK_SOURCE_TX = “001”,
“010, “011”, “100”, or “101”)
Note that if UDF_HS=1 in the
HS_LIN_REG, TL_CLK[7:1] should be
tied high.
Transmit Signaling Mirror is a copy of
the TL_SIG output. In Direct mode, if
CLK_SOURCE_TX=”111” then
signaling is output on this pin. This
option is used with devices that share
the same pin for clock and signaling.
In this mode CTL_CLK is used as the
line clock.
Maximum output current (IMAX) = 6
mA.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
52
PMC [ PMC-SIERRA, INC ]
