RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
CTL_CLK
Input
C16
Common Transmit Line Clock is a
transmit line clock which can be
shared across all lines. Whether this
clock is used or not for a given line is
dependent on the value of
CLK_SOURCE_TX in the
LINE_STR_MODE memory register for
that line.
RL_SYNC[7]
RL_SYNC[6]
RL_SYNC[5]
RL_SYNC[4]
RL_SYNC[3]
RL_SYNC[2]
RL_SYNC[1]
RL_SYNC[0]
Input
B21
C20
F19
J19
M20
P20
U22
W20
Receive Line Synchronization 7 to 0
are the receive frame synchronization
indicators used in SDF-MF and SDF-
FR modes. Depending on the value of
MF_SYNC_MODE in the
LI_CFG_REG register for the line,
these signals either indicate a frame
boundary or a multi-frame boundary.
Tie to ground if unused.
RL_DATA[7]
RL_DATA[6]
RL_DATA[5]
RL_DATA[4]
RL_DATA[3]
RL_DATA[2]
RL_DATA[1]
RL_DATA[0]
Input
Input
Input
D20
E22
H20
K20
N19
R19
T20
AB22
Receive Line Serial Data 7 to 0 carries
the receive data from the
corresponding framer devices.
RL_SIG[7]
RL_SIG[6]
RL_SIG[5]
RL_SIG[4]
RL_SIG[3]
RL_SIG[2]
RL_SIG[1]
RL_SIG[0]
B20
C22
G21
J21
M22
P22
T22
Y21
Receive Line Signaling 7 to 0 carries
the CAS data from the corresponding
framer devices.
RL_CLK[7]
RL_CLK[6]
RL_CLK[5]
RL_CLK[4]
RL_CLK[3]
RL_CLK[2]
RL_CLK[1]
RL_CLK[0]
A21
E21
G22
J22
L22
P21
T21
AA22
Receive Line Clock 7 to 0 is the clock
received from the corresponding
framer device used to clock in
RL_DATA, RL_SIG, and RL_SYNC.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
53
PMC [ PMC-SIERRA, INC ]
