RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Register 0x81010: A1SP Interrupt Register (A1SP_INTR_REG)
Bit
Type
Function
Default
15
14
13
12
11
10
9
RO
RO
Unused
Unused
X
X
X
X
X
X
X
X
X
0
RO
Unused
RO
Unused
RO
Unused
RO
Unused
RO
Unused
8
RO
Unused
7
RO
Unused
6
R2C
R2C
R2C
R2C
R2C
R2C
R2C
TALP_FIFO_FULL
RSTAT_FIFO_FULL
RSTAT_FIFO_EMPB
TIDLE_FIFO_FULL
TIDLE_FIFO_EMPB
OAM_INTR
5
0
4
0
3
0
2
0
1
0
0
FR_ADV_FIFO_FULL
0
The bits in this register are set upon entry into the indicated condition and are
cleared when this register is read. If any of these conditions still exist the
corresponding bit will not be set again until the condition ends and then occurs
again. Read A1SP_STAT_REG for current status. If any bit is set in this register
and the corresponding enable bit is set in A1SP_INTR_EN_REG, the
A1SP_INTR bit will be set in MSTR_INTR_REG.
FR_ADV_FIFO_FULL
When set indicates the Frame Advance FIFO has entered the full state since
the last time this register was read. On read:
0) Frame Advance FIFO has not entered the full state
1) Frame Advance FIFO has entered the full state
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
261
PMC [ PMC-SIERRA, INC ]
